The logical sum of the minterms associated with a Boolean function specifies the conditions under which the function is equal to 1. The function is equal to 0 for the rest of the minterms.
In practice, in some applications the function is not specified for certain combinations of the variables.
Example: To represent 10 decimal numbers (0-9) using binary we need 4 bits, but this leads to 6 combinations being unused i.e. from 1010 - 1111
It is customary to call the unspecified minterms of a function don't-care conditions. These don't-care conditions can be used on a map to provide further simplification of the Boolean expression
A don't-care minterm is a combination of variables whose logical value is not specified. Such a minterm is marked with a X
In choosing adjacent squares to simplify the function in a map. the don' t-care minterms may be assumed to be either 0 or 1. When simplifying the function. we can choose to include each don't-care minterm with either the 1's or the 0's depending on which combination gives the simplest expression.
Q. Simplify the Boolean function F(w, x, y, Z) = ∑(1,3,7,11,15) which has the don't-care conditions d( w,x,y,z)= ∑ ( 0 ,2 ,5 )
The minterms of F are the variable combinations that make the function equal to 1. The minterms of d are the don't-care minterms which are marked as X.
To get the simplified expression in sum-of-products form, we must include all five 1's in the map, but we may or may not include any of the X's, depending on the way the function is simplified.
In part (a) of the diagram, don't-care minterms 0 and 2 are included with the 1's, resulting in the simplified function: F = yz + w'x'
In part (b) don' t-care minterm 5 is included with the 1's and the simplified function is now F = yz + w'z
Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all the digital logic families.
NAND gate and NOR gate are universal gates because any digital system can be implemented with them
The Exclusive-OR (XOR) denoted by the symbol ⊕ is a logical operation that performs the following Boolean operation:
x ⊕ y = x'y + xy'
The Exclusive-OR is equal to 1 if only x is equal to 1 or if only y is equal to 1 but not both.
The Exclusive NOR also known as equivalence performs the following Boolean operation:
(x ⊕ y)' = xy + x'y'
The Exclusive-NOR is equal to 1 if both x and y are equal to 1 or if both are equal to 0. The Exclusive-NOR can be shown to be the complement of the Exclusive-OR
The following identities apply to the Exclusive-OR operation:
x ⊕ 0 = x
x ⊕ 1 = x'
x ⊕ x = 0
x ⊕ x' = 1
x ⊕ y' = x' ⊕ y = (x ⊕ y)'
Exclusive-OR operation is both commutative and associative: .
A ⊕ B = B ⊕ A
(A ⊕ B) ⊕ C = A ⊕ ( B ⊕ C ) = A ⊕ B ⊕ C
Exclusive-OR is particularly useful in arithmetic operations and error detection and correction circuits.
A multiple variable Exclusive-OR function is a gate with three or more inputs.
Such a gate gives output high if any odd number of inputs are high. Therefore it is known as an Odd function. This is contrary to the two variable case, in which only one variable must be equal to 1.
The boolean function of a three variable EX-OR is:
A ⊕ B ⊕ C = ( AB' + A' B)C' + ( AB + A' B' )C
= AB' C' + A' BC' + ABC + A' B' C
You can see that in each of the minterms only an odd number of inputs are one. The remaining four minterms not included in the function are 000, 011 , 101 , and 110 and they have an even number of 1's in their binary numerical values.
In general, an n-variable exclusive-OR function is an odd function defined as the logical sum of the 2n / 2 minterms whose binary numerical values have an odd number of 1's.
A ⊕ B ⊕ C ⊕ D = ∑( 1, 2, 4, 7, 8, 11, 13, 14)
A parity bit is used for the purpose of detecting errors during the transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1's either odd or even.
The message, including Ihe parity bit, is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted.
The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that checks the parity in the receiver is called a parity checker.
Suppose we consider even parity, and the signal is of size three bits x, y, z and the parity bit is P. Then the parity bit value is such that the nmber of bits in the total message (message + parity) is equal to even.
A truth table drawn for the above scenario is equivalent to the truth table of the EX-OR function: (x ⊕ y ⊕ z)
On the receiving end, a parity checker has 4 inputs (x, y, z, P) and has to see whether the message has even number of 1's or not. This scenario can be implemented using a 4 input EXOR gate (x ⊕ y ⊕ z ⊕ P)